A programmable logic device (PLD), such as for example a field programmable gate array (FPGA) or a complex programmable logic device (CPLD), generally has an array of logic blocks that may be connected via a programmable routing structure. For example, an FPGA may have logic blocks that include look-up tables, multiplexers, and registers (e.g., flip-flops). Because many customer designs require synchronized circuits, the typical FPGA also provides one or more low and/or zero skew clock distribution networks (also known as clock trees) to drive the clock inputs of the logic blocks.
After place and route of the user's design, the maximum frequency of the design may be calculated based on the maximum logical path delays between registers of the logic blocks. Clock boosting techniques (also referred to as clock cycle stealing) may also be applied, which for example introduce clock skew to increase timing margins. However, conventional approaches to clock boosting typically include special circuit components (i.e., hardware) within the PLD, such as additional clock distribution networks or special programmable delay elements. These conventional approaches typically result in additional manufacturing costs, require additional silicon area to implement, and/or reduce the logic density or increase the size of the PLD.
As a result, there is a need for improved clock boosting techniques for PLDs.